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Extra resources for AN 08-10-112 BC-348-J,N,Q Radio Receiver (maintenance)
44 = 1-54 X / a . c . POWER SUPPLY CONFIGURATIONS—cont. c. c. / d . c = 0-28 X / » . c. c. = 0 9 0 X F a . c . c. = 0 9 0 X / a . c . 0-64 X / a . c Vdc. c. = 0-45 x Vc / d . c . = 1-27 X / a . c. gain / = low frequency e\ = input voltage — 3 dB point e0 = output voltage Rm = input i mpedance Split supply configurations—supply connections omitted for clarity. c. c. amplifier £Rl < R 3 ill ill 2nRiCi 2nRiC2 Non-inverting buffer 2TTRICI Inverting buffer R, 2nRlC\ R, fo = 46 2nRLCi OP-AMP STANDARD CIRCUITS—cont.
In odd parity sum of data Is + parity 1 is odd. Propagation delay—Time taken for signal to pass through a device, limits highest frequency of operation. Quad—Four. Quiescent—stable state not driving a load. Schmitt trigger—Circuit with hysteresis. Synchronous—Operation dependent on clock pulses. LOGIC TERMINOLOGY The logic symbols used to represent the MSI devices follow Mil Std 806B for logic symbols. MSI elements are represented by rectangular blocks with appropriate external AND/OR, gates when necessary.
Per Supply voltage package mW Decoupling Logic Nomina* Min. Max. and other (typ) V V family V requirements No special precautions No special precautions No special 30 4-5 5-5 DTL 50 precautions 4-75 5-25 40. 01μΡ 74 Series 50 ceramic cap 4-75 5-25 60 74H 50 acitor for Series every 8 4-75 5-25 40 74S 50 > packages to Series 4-75 5-25 8 eliminate 74LS 50 switching Series > current spike. 0· 31 No special CMOS — 3 0 180 precautions RTL and DTL have been superseded e ither by CMOS (up to 5 MHz) or TTL for higher speed s.